21 lines
553 B
Tcl
21 lines
553 B
Tcl
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proc load_design {libs lefs design netlist def sdc} {
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foreach libFile $libs {
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read_liberty $libFile
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}
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foreach lef $lefs {
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read_lef $lef
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}
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# read_verilog $netlist
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# link $design
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read_def $def
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#read_spef $spef
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#read_db $odbf
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read_sdc $sdc
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#set_propagated_clock [all_clocks]
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# Ensure all OR created (rsz/cts) instances are connected
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# add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
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# add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
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# global_connect
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}
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