From 50897f14dc37c624f1f31f0e826cfe0b2e7ff296 Mon Sep 17 00:00:00 2001
From: liulixinkerry <kerryliu1997@gmail.com>
Date: Mon, 29 Apr 2024 11:09:45 +0800
Subject: [PATCH] partially support verilog

---
 README.md                             |  5 ++---
 cpp_to_py/common/db/Database.cpp      |  8 ++++----
 cpp_to_py/common/io/file_verilog.cpp  | 11 ++++++++++-
 cpp_to_py/io_parser/PyBindCppMain.cpp |  7 +++----
 4 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/README.md b/README.md
index bae4f1f..6e312ef 100644
--- a/README.md
+++ b/README.md
@@ -110,12 +110,11 @@ Suppose there is a LEF/DEF benchmark named `toy` in `data/raw`, you can use the
 python main.py --custom_path lef:data/raw/toy_input.lef,def:data/raw/toy_input.def,design_name:toy,benchmark:test --load_from_raw True --detail_placement True
 ```
 
-You can also use the argument `--custom_json` to run multiple LEFs + DEF:
+You can also use the argument `--custom_json` to run multiple LEFs + DEF + Verilog:
 ```
 python main.py --custom_json examples/examples.json --load_from_raw True --target_density 0.9
 ```
-Please provide your LEFs/DEF in the input `json` file. An example of [ASAP7](https://github.com/The-OpenROAD-Project/asap7) input is given in `./examples/examples.json`.
-
+Please provide your LEFs/DEF in the input `json` file. An example of [ASAP7](https://github.com/The-OpenROAD-Project/asap7) input is given in `./examples/examples.json`. Note that the `verilog` format is only partially supported.
 
 ## Load design from preprocessed `pt` file (Optional)
 The following script will dump the parsed design into a single torch `pt` file so Xplace can load the design from the `pt` file instead of parsing the input file from scratch. 
diff --git a/cpp_to_py/common/db/Database.cpp b/cpp_to_py/common/db/Database.cpp
index a2bc944..dda5b5f 100644
--- a/cpp_to_py/common/db/Database.cpp
+++ b/cpp_to_py/common/db/Database.cpp
@@ -53,10 +53,10 @@ void Database::load() {
         readConstraints(setting.Constraints);
     }
 
-    // verilog is unused now
-    // if (setting.Verilog != "") {
-    //     readVerilog(setting.Verilog);
-    // }
+    if (setting.Verilog != "") {
+        readVerilog(setting.Verilog);
+    }
+
     logger.info("Finish loading rawdb");
 }
 
diff --git a/cpp_to_py/common/io/file_verilog.cpp b/cpp_to_py/common/io/file_verilog.cpp
index dc7a040..d956730 100644
--- a/cpp_to_py/common/io/file_verilog.cpp
+++ b/cpp_to_py/common/io/file_verilog.cpp
@@ -72,6 +72,7 @@ bool readVerilogLine(istream &is, vector<string> &tokens) {
 }
 
 bool Database::readVerilog(const std::string &file) {
+    logger.info("Reading verilog...");
     ifstream fs(file.c_str());
     if (!fs.good()) {
         logger.error("cannot open verilog file: %s", file.c_str());
@@ -120,7 +121,7 @@ bool Database::readVerilog(const std::string &file) {
             }
         }
 
-        if (tokens.back() == ";") {
+        if (!tokens.empty() && tokens.back() == ";") {
             tokens.pop_back();
             finished = true;
         }
@@ -134,7 +135,12 @@ bool Database::readVerilog(const std::string &file) {
                 if (!iopin) {
                     logger.error("io pin not found: %s", pinName.c_str());
                 }
+                Pin* pin = iopin->pin;
+                iopin->is_connected = true;
                 Net *net = addNet(pinName);
+
+                pin->net = net;
+                pin->is_connected = true;
                 net->addPin(iopin->pin);
             }
         } else if (status == StatusWire) {
@@ -151,8 +157,11 @@ bool Database::readVerilog(const std::string &file) {
                 string netName(tokens[3 + i * 2]);
                 Pin *pin = cell->pin(pinName);
                 Net *net = this->getNet(netName);
+                pin->net = net;
                 net->addPin(pin);
+                pin->is_connected = true;
             }
+            cell->is_connected = true;
         }
     }
 
diff --git a/cpp_to_py/io_parser/PyBindCppMain.cpp b/cpp_to_py/io_parser/PyBindCppMain.cpp
index 3205753..4766bd2 100644
--- a/cpp_to_py/io_parser/PyBindCppMain.cpp
+++ b/cpp_to_py/io_parser/PyBindCppMain.cpp
@@ -47,10 +47,9 @@ bool loadParams(const py::dict& kwargs) {
         return false;
     }
 
-    // verilog is unused now
-    // if (kwargs.contains("verilog")) {
-    //     db::setting.Verilog = kwargs["verilog"].cast<std::string>();
-    // }
+    if (kwargs.contains("verilog")) {
+        db::setting.Verilog = kwargs["verilog"].cast<std::string>();
+    }
 
     // ----- other options -----