#pragma once #include #include #include #include #include #include "EnumNameMap.h" #include "Helper.h" #include "tokenizer.h" #include "unit.h" #include "Lut.h" using std::optional; using std::string; using std::unordered_map; using std::variant; using std::vector; namespace db { class Database; class CellType; }; // namespace db namespace gt { class CellLib; class LibertyCell; class LibertyPort; class TimingArc; struct LutTemplate; class Lut; class BusType; class InternalArc; // class LutVar; enum class DelayModel { generic_cmos, table_lookup, cmos2, piecewise_cmos, dcm, polynomial, unknown }; enum class CellPortDirection { input, output, inout, internal, unknown }; DelayModel findDelayModel(const std::string model_name); CellPortDirection findPortDirection(const std::string dir_name); class CellLib { public: ~CellLib() { logger.info("Destruct celllib"); } CellLib() = default; CellLib(db::Database *rawdb_) : rawdb(rawdb_) {} db::Database *rawdb = nullptr; db::CellType *cell_type_ = nullptr; using token_iterator = std::vector::iterator; DelayModel delay_model; string name; optional time_unit_; optional power_unit_; optional resistance_unit_; optional capacitance_unit_; optional current_unit_; optional voltage_unit_; optional energy_unit_; unordered_map> default_values = { {"default_cell_leakage_power", optional{}}, {"default_inout_pin_cap", optional{}}, {"default_input_pin_cap", optional{}}, {"default_output_pin_cap", optional{}}, {"default_fanout_load", optional{}}, {"default_max_fanout", optional{}}, {"default_max_transition", optional{}}, {"voltage", optional{}}, }; unordered_map scale_factors = { {"time", 1.0}, {"resistance", 1.0}, {"power", 1.0}, {"capacitance", 1.0}, {"current", 1.0}, {"voltage", 1.0}, {"energy", 1.0} }; unordered_map Bus_types_; unordered_map lut_templates_; unordered_map lib_cells_; unordered_map> func2libcell_map; LutTemplate *get_lut_template(const string &); LibertyCell *get_cell(const std::string &name); void read(const string &file); void finish_read(); void finish_port_read(LibertyPort *liberty_port); float lut_index_to_scale_factor(LutVar var) { switch (var) { case LutVar::CONSTRAINED_PIN_TRANSITION: case LutVar::INPUT_NET_TRANSITION: case LutVar::RELATED_PIN_TRANSITION: case LutVar::INPUT_TRANSITION_TIME: return scale_factors["time"]; case LutVar::TOTAL_OUTPUT_NET_CAPACITANCE: return scale_factors["capacitance"]; case LutVar::NORMALIZED_VOLTAGE: return scale_factors["voltage"]; default: throw std::invalid_argument("Invalid LutVar value"); } } public: LibertyCell *extractLibertyCell(token_iterator &, const token_iterator); LibertyPort *extractLibertyPort(token_iterator &, const token_iterator, LibertyCell *); void extractLibertyBus(token_iterator &, const token_iterator, LibertyCell *, LibertyPort *); TimingArc *extractTimingArc(token_iterator &, const token_iterator, LibertyPort *); InternalArc *extractInternalArc(token_iterator &, const token_iterator, LibertyPort *); std::optional extract_operating_conditions(token_iterator &itr, const token_iterator end); LutTemplate *extract_lut_template(token_iterator &, const token_iterator); Lut *extract_lut(token_iterator &, const token_iterator, float value_scale); BusType *extract_bus_type(token_iterator &, const token_iterator); void apply_default_values(); void uncomment(std::vector &); void tokenize(const std::vector &, std::vector &); }; class LibertyCell { public: LibertyCell() = default; string name; db:: CellType *cell_type_ = nullptr; vector ports_; vector buses_; // map ports_map_; map ports_map_; vector leakage_powers_; optional leakage_power_; optional area_; bool is_seq_ = false; int num_bits_ = 0; public: int get_port(const std::string &name); }; class LibertyPort { public: LibertyPort() = default; public: string name; LibertyCell *cell_; CellPortDirection direction_; optional port_capacitance_[3]; bool is_clock_ = false; bool is_bundle_ = false; // bool is_bus_ = false; vector member_ports_; vector timing_arcs_; vector internal_arcs_; map timing_arcs_map_; vector timing_arcs_non_cond_non_bundle_; map internal_arcs_map_; vector internal_arcs_non_cond_non_bundle_; optional function; // optional capacitance; // optional fall_capacitance; // optional rise_capacitance; optional fanout_load; optional max_fanout; optional min_fanout; optional max_capacitance; optional min_capacitance; optional max_transition; optional min_transition; }; class BusType { public: BusType() = default; std::string name; optional bit_from; optional bit_to; optional bit_width; optional downto; }; }; // namespace gt